Raised-cosine Filter

After generating data, the QPSK signal is passed through a polyphase finite impulse response (FIR) interpolator (as seen in the block diagram).  A common signal distortion in communication system is inter-symbol interference (ISI)  among adjacent symbols.  The ISI degrades system performance unless properly corrected using channel equalization. In the QPSK system, the FIR filter generates raised-cosine pulses, which suppress the ISI.  After being interpolated, the data is modulated by 12.5 MHz sine and cosine carriers and then sent through the channel. The received signal is down-converted and decimated for demodulation. The decimator utilizes the same FIR filter coefficients as the interpolator.
    Xilinx block set provides an FIR filter block for filter design. It uses distributed arithmetic structure. For the QPSK system which is inherently a multirate signal processing system, the distributed arithmetic FIR design is not an efficient implementation in terms of hardware resource and processing speed. A polyphase structure is used instead.  The polyphase FIR raised-cosine filter is an efficient method used to interpolate and decimate, especially in a discrete-time system using an FPGA development system.  It reduces the hardware resource and processing delay significantly.