E-SNIFF: The Embedded Ethernet Packet Sniffer
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HARDWARE

The E-sniff project is implemented entriely in an Altera Cyclone II FPGA and uses a Nios II Soft CPU core as its Central Processing Unit. To save processor time, special-purpose hardware is used to handle interaction with the user. The VGA monitor is driven by special-purpose hardware that maps ASCII character codes from an on-chip memory to the screen. Using this method, the CPU can simply write characters to memory to display them on the monitor. A novel line-return system enables the CPU to do a line return in three instruction cycles by adding a hardware offset to the displayed text. The keyboard controller is also implemented in hardware. It write received characters directly to the bottom line of the screen without interrupting the processor. When the enter key is pressed, the CPU is interrupted and reads the input out of the bottom line of the display memory, then clears the prompt so the user can enter another command. In this way, the CPU does not have to bother with processing individual keystrokes or driving the HSYNC and VSYNC lines of the VGA interface, leaving more CPU time for the critical task of packet processing.

Download the completed active serial programming file below.

Download the most recent stable version of the E-Sniff Hardware: E_SNIFF_v2.0_RELEASE