PPT Slide
Jarrod Luker Tim McKinney
TESTABLE VLSI CIRCUIT DESIGN FOR CELLULAR ARRAYS
PREVIOUS WORK
DESIGN / SIMULATION
Logic Works
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PSPICE
PATENTS / STANDARDS
Patent #US5173906: Built-in test for integrated circuits
Patent #US5301199: Built-in self test circuit
Patent #US5790562: Circuit with built-in test and
method thereof
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