PPT Slide
Jarrod Luker Tim McKinney
TESTABLE VLSI CIRCUIT DESIGN FOR CELLULAR ARRAYS
The main objective of this project is to design testability features that can potentially be included in any CMOS chip. This project will consist of a testable circuit and on-chip features to test the circuit. The testable circuit is a 4-bit x 4-bit multiplier designed using a cellular array. The features to test the circuit include a sequence generator and an 8-bit register.