Digital Signal Processor
using FPGA and VLSI technology

Project By:
Jeremy Barsten
Jeremy Stockwell

Project Advisors:
Dr. Vinod B. Prasad - info
Dr. Thomas L. Stewart - info

Deliverables       Summary:  The purpose of this project is to construct ahigh-speed, application-specific digital signal
Links:                   processor usingboth FPGA and VLSI technology.  This project willuse the Xilinx board and a
                              specifically fabricated ASIC chip to create the individual components neededto realize this

Project                   processor.  For more description, see the links on the left of thispage.
Memo -
   PDFFile           Progress:
                           By 1-22-03:  Done investigating the delays and timing of theFPGA board.  Determined the adder
Functional                and multiplier to be used in the project.  Continued VHDL and VLSIdesign of the adder and
Description-            multiplier.
   PDFFile           By2-4-03:  Finished the VLSI design of the ripple-carry adder. Tested it fully by using L-Edit Pro
                               and PSpice.  Also, VHDL design of the signed adder and multiplierfinished.  Both were tested using
Complete System    ModelSim and Leonardo Spectrum. Design and testing also done for the 4-bit by 4-bit multiplier to
Block Diagram-       be implemented in VLSI.  To see the LogicWorks design of the multiplier,click here.
  PDF File           By 2-18-03:  Finishing up VHDL coding for the multiplier, adder,and memory storage for the processor
                                 to be flashed on the FPGA board.  Will test the function of the processorby simulating it using
Preliminary                ModelSim and checking the answers in MATLAB.  Also, the VLSI designof the 4-bit by 4-bit
 Presentation             multiplier has been completed.  To view the VLSI layout of the singlemultiplier cell, click here.  For
                                 the entire layout of the CMOS multiplier, click here.
Proposal -          By2-25-03:  Ran into trouble with the data on the FPGA board. We were receiving one more sign bit
   HTML File            than originally thought.  Began to troubleshoot the VHDL code andcontinue testing the processor using
   PDF File                ModelSim and MATLAB.  Also, began and continued to work on CMOS circuitryin L-Edit Pro that
                                 would make the multiplier 2's complement ready.  Began to design anddevelop these stages for both
Final                          the input and output of the multiplier.
                         By 3-4-03:  Completed the CMOS circuitry for the inputs ofthe multiplier to make it 2's compliment ready.
Final                         The L-Edit design of this circuit can be seen by clicking here.  Beganwork on the output circuitry from
  Report                    the multiplier to handel 2's compliment output values.  Also, continuedtroubleshooting the VHDL code
                                 for the extra sign bit.  Once completed, a bit file will be createdto download the entire design to the
                                 Xilinx FPGA expansion board (version II) designed in a previous project. (To view the Expansion
                                 Borad projcect, click here.)

                         By 3-11-03:  Continued working on the output adjustment CMOScircuitry in L-Edit Pro.  Also, the bit file
                                 was created to begin preliminary testing of the processor on the Xilinxexpansion board.

                         By 3-25-03:  Finished the design of the CMOS adjustment circuitryfor the multiplier.  Connected all of the
                                 adjustment circuits (both input and output) to the multiplier and testedit using both positive and negative
                                 binary numbers in PSpice.  Will begin work on the data managementportion of the processor design
                                 once the simulation of the multiplier is complete.  For a full viewof the signed 5-bit multiplier, click here.

                          By 4-1-03:  Finished the simulation of the signed multiplierand began work on designing the glue logic
                                  required in the data management portion of the CMOS processor.  Also,ran simulations in MATLAB
                                  to test the simulated results of the processor coded in VHDL (using ModelSim)to the theoretical
                                  results found in MATLAB.  To see the results, click here.

                          By 4-8-03:  Continued to work on the data management portionof the VLSI processor.  Finished the design
                                  of the registers designed in VLSI used to store the coefficients and previouslycomputed values.  To
                                  view the design, click here.  Also, beganto design CMOS circuitry that would control the cycles used
                                  in the VLSI processor.  This circutiry consisted of a cascade of D-typeflip-flops.  Encountered
                                  problems with the FPGA board and began to troubleshoot.  Checked thecapabilities of the on-board
                                  D/A and A/D converters to see what application we could use to demonstrateour FPGA processor.

                          By 4-15-03:  Finished the CMOS circuitry for the clock-managementcircuitry that would control the cycles
                                  of the VLSI processor.  The final CMOS circuit can be seen by clickinghere. Began to put all of the
                                  components together in L-Edit Pro to make the entire VLSI processor. Continued to troubleshoot the
                                  FPGA processor and investigate the on-board converters.

                            -  To view the Xilinx website (where you can get information the FPGAboard and download an eval
                                 version of ModelSim), click here.

                            -  To view Bradley University's Electrical Engineering departmentWebsite, click here.
                            -  To view the PDF files, you will need Adobe Acrobat reader. If you don't have Reader, click here
                                 to download it.