VHDL Code For The Remote Unit
(This code can also be seen in the final report appendices section)
-- Re_enable has been commented out because it is not a necessary signal for the code.
-- The purpose of re_enable was to have a second reset so that rst_n could be a main reset
-- and re_enable could be a user reset.
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity shftreg is
port
(
clk,rin,enable : in std_logic; -- 2KHz clk input
rst_n : in std_logic;
TTL_out : out unsigned(1 downto 0)
--Q : buffer std_logic_vector(8 downto 0);
);
end shftreg;
architecture smy of shftreg is
signal IQ : std_logic_vector(8 downto 0);
signal TTL_out_w : unsigned(1 downto 0);
signal clk_w : unsigned(3 downto 0);
signal sampler : unsigned(3 downto 0);
signal test_start : unsigned(3 downto 0);
signal bit_counter : unsigned(3 downto 0);
signal latch_out : std_logic;
signal retest_start : std_logic;
signal sample : std_logic;
signal load : std_logic;
signal inc : std_logic;
signal start_bit : std_logic;
signal clr : std_logic;
signal check_compare : std_logic;
signal slow_clk : std_logic;
begin
-- Clock Generation Circuitry
process(rst_n,clk)
begin
if (rst_n = '0') then
clk_w <= (others => '0');
elsif rising_edge(clk) then -- produces a 16 times slower clock for the
clk_w <= clk_w + 1; -- shift register, compare, TTL output code
end if;
end process;
slow_clk <= clk_w(3);
-- Start Bit Detection
process(rst_n,clr,clk)
begin
if rst_n = '0' then
start_bit <= '1';
elsif rising_edge(clk) then
if (rin = '0') then -- latches start_bit low when input drops low
start_bit <= '0';
elsif (clr = '0') then -- resets latch when clr = 0
start_bit <= '1';
-- elsif (re_enable = '0') then
-- start_bit <= '1';
end if;
end if;
end process;
-- UART Circuitry
process(clk, rst_n)
begin
if (rst_n = '0') then
test_start <= (others => '0');
sampler <= "0001";
sample <= '0';
load <= '1';
inc <= '0';
bit_counter <= "0110"; -- set bit_counter to 5 to count all 10 bits
check_compare <= '0';
clr <= '1';
retest_start <= '1';
elsif rising_edge(clk) then
clr <= '1';
-- if (re_enable ='0') then
-- test_start <= (others => '0');
-- sampler <= "0001";
-- sample <= '0';
-- load <= '1';
-- inc <= '0';
-- bit_counter <= "0110";
-- check_compare <= '0';
-- clr <= '1';
-- retest_start <= '1';
-- end if;
if start_bit = '0' then
if (retest_start = '1') then
if (load = '1') then
test_start <= "1000";
load <= '0';
elsif (test_start = "1111" and rin = '0') then
sample <= '1';
retest_start <= '0';
elsif (test_start = "1111" and rin /= '0') then
--RESET the start bit latch above
clr <= '0';
load <= '1';
else
test_start <= test_start + 1;
end if;
end if;
if (sample = '1') then -- count 16 times then sample bit
sampler <= sampler + 1; end if;
if (sampler = "0100") then -- limits check_compare clk period
check_compare <= '0'; end if;
if (sampler = "1111") then -- counts 9 bits
bit_counter <= bit_counter + 1; end if;
if (bit_counter = "1111" and rin = '1') then
-- all bits have been counted and
-- stop bit = 1
check_compare <= '1'; -- allows for comparing in shift
-- register
-- RESETS
clr <= '0'; -- resets the start-bit latch
load <= '1'; -- resets test_start
sample <= '0'; -- stops sampler counting
retest_start <= '1'; -- activates the start-bit sampler
bit_counter <= "0110"; -- resets bit_counter
elsif (bit_counter = "1111" and rin /= '1') then
-- all bits have been counted
-- and stop-bit not = 1
-- RESETS -- same resets as above
clr <= '0';
load <= '1';
sample <= '0';
bit_counter <= "0110";
retest_start <= '1';
end if;
end if;
end if;
end process;
-- Shift Register Circuitry
process(slow_clk,rst_n)
begin
if rst_n = '0' then
IQ <= (others => '0');
elsif rising_edge(slow_clk) then
case enable is
when '0' => null;
when '1' => IQ <= IQ(7 downto 0) & rin; -- shifts the bits through
-- the register(MSB first)
when others => null;
end case;
-- if (re_enable = '0') then
-- IQ <= (others => '0'); -- resets register if re_enable = 0
-- end if;
end if;
Q <= IQ;
end process;
-- Latch Circuitry\Compare Circuitry
process(rst_n,slow_clk)
begin
if rst_n = '0' then
latch_out <= '0';
elsif rising_edge(slow_clk) then
-- if (re_enable = '0') then
-- latch_out <= '0'; -- resets latch if re_enable = 0
if (IQ = "000000001" and check_compare = '1') then
-- compares input to preset ID code
latch_out <= '1'; -- holds TTL output high until reset by user
elsif (IQ = "000000001" and check_compare = ‘1’) then
latch_out <= ‘0’; --turns audible tone off when user presses
--button on the base unit
end if;
end if;
end process;
-- TTL Output Generation Circuitry
process(rst_n, TTL_out_w, clk) is
begin
if(rst_n = '0') then
TTL_out_w <= (others => '0');
elsif rising_edge(clk) then
if(latch_out = '1') then
TTL_out_w <= TTL_out_w + 1; -- creates TTL output wave to
end if; -- speaker for tone generation
end if;
end process;
TTL_out <= TTL_out_w;
end smy;