11/01/2001
Created initial schematic for Ethernet Transceiver. Began parts lists, and started looking for vendors for parts.

11/08/2001
Finished necessary parts list and found vendors. Began EMAC board interface design.

11/15/2001
Finished initial hardware design and loading analysis. Began timing analysis. Once this is completed the hardware design portion will be done.

11/29/2001
Completed timing analysis, so hardware design is complete. Began writing code to interface with chip.

12/6/2001
Wrote code to check for a new packet. Presented proposal to advisor and DRT.

1/24/2002
Gathered parts together and prepared to assemble. Wrote code to read the received packet into a buffer. Created structures to define Ethernet packet, and map the received packet buffer to the structures. Wrote code to decide what type of packet has been received.

1/31/2002
Began assembling parts on wire wrap board.

2/7/2002
Continued construction of the hardware. I tested the Ethernet side and it did not work, so I need to do some debugging there. I also started putting together the EMAC board side, and should be able to test that this next lab period.

2/14/2002
Wired the connection of the CS8900A to the EMAC board.

2/21/2002
Finished wiring connection to the EMAC board. Worked on code to process ICMP packet.

2/28/02
Completed ICMP packet processing code. Tested connecting the CS8900A to the EMAC board, and some loading occured. Will debug next time.

3/7/02
Wrote ARP processing code. Wrote code to process a UDP packet and send a response. Resolved loading issue. Still no response from CS8900A chip however.

3/14/02
Worked on getting a response from the CS8900A chip. Attempting to try a boundary test scan to test chip.