Bradley University's Lab system is designed for students to work on every tuesday.

11/7/00
    Nandor - Made the address decode in logic level design.
                        a) used an all "and" gate design
    Ryan - Worked on the flip flop in logic level design.

11/14/00
    Nandor - Made the VLSI design of a CMOS NAND and NOR
                   gate.
    Ryan - Worked on the flip flop errors. Also, started the VLSI
                design of the D flip flop.

11/21/00 - Break

11/28/00
    1) Half the day was spent working on the presentation
    2) 2nd half:
            Nandor - Designed the storage component of the memory.
            Ryan - Changed the address decoder.

1/30/01
    1) We finalized the design of the address decoder.
    2) Finalized the actual layout of the storage section.
    3) Got the MOSIS pad and checked how to use it's connecitons.

2/6/01
    1) Made the design for the tri-state buffer.
    2) Implemented the buffer into VLSI.
    3) Ran a PSPICE analysis on it.
    4) Shrunk the address decoder.

2/13/01
    1) Redesign flip flop
        a) The old one took too much pad space.
    2) Connected all the grounds and Vdd's on the address decoder.

2/20/01
    **Today we noticed that 64 bits was too large to fit onto our design.
    **The project has been compressed to a 30-bit memory block.
    1) Finished the address decoder for 64-bit
        a) Started to work on a 2x4 decoder for the pad
    2) Tested the buffer and flip flop storage element.