The FPGA Tutorial

We'll start out with assuming that you wrote your code already and have it saved under a .vhd file.
(for the tutorial, we'll use example.vhd)

Testing , Implemntation

Now, before you put the program onto the chip, you're going to want to test it.

Testing Portion:
1) In Mentor Graphics, go to the terminal window.
(this will appear)

cegt201 1>

2) Next, type vcom then example.vhd and hit enter.

cegt201 1> vcom example.vhd

3) If you didn't recieve any errors, you could move onto the next portion.
    a) If you did recieve errors, "vcom" tells you what lines the errors are on. (the red text)

4) Type vsim and hit enter

cegt201 2> vsim

5) A dialog box will appear that is called: "Welcom to ModelSim 5.3a"
6) Click on done and a box will appear with the options of what programs to run, choose yours and hit "load".
7) You will recieve a terminal window again that says VSIM


8) Type "view signals" and hit enter, another box will pop up.

VSIM 1> view signals

9) Set your inputs here by using the clock of force commands in the edit menu.
10) To test, you want to select your signals.
    a) For every signal click "view" then "wave" then "selected signal." Another box will pop up.
11) After you choose all the signals you want to run, click on the "run" picture. (white box at end of menu)
12) If all the outputs run right, it's time to move onto the implementation.

1) Go back to terminal window

cegt201 3>

2)  Type "leonardo" and hit enter.

cegt201 3> leonardo

3) Just hit "ok" when the window pops up for license check.
4) Select your output file, but selecting the VHDL code you want to download
5) Then select the chip that you are going to download too.
6) Set the speed that you wish to operate at.
7) Click on "Run Flow".  This will produce a .edf file.
8) If you want you can click on the "view RTL diagram" this will show you the gates that the code created.
9) Now that you have the .edf file, you need to open it up in Xilinx Design Manager.
10) Under design on the toolbar click on implement.
11) After the file is implemented go to Utilities -> Constraint Manager.
12) Click on Ports and set the ports for your input and outputs.
13) After all the ports are assigned reimplement the file.
14) Now that the file is reimplemented go to the g:\xstools\bin> directory.
15) Type xsload c:where_your_bit_file_is_stored\name_of_file.bit
16) This will load your bit file into the FPGA.