Testable VLSI Circuit Design for Cellular Arrays
Jarrod Luker and Tim McKinney
Advisor: Dr. V. Prasad
The objective of this project is to design a system based on cellular arrays with testing features that can be fabricated on a chip so that the main function of practically any CMOS chip can be tested with a minimal amount of external hardware or software.
This type of design includes the use of CMOS technology and logic gate
design. In this project a 3-bit x 3-bit multiplier circuit was designed
to be tested using the cellular array concept. A 3-bit sequence generator
and a 6-bit register were designed on the chip as testing features. When
these features are enabled they will test the functionality of the 3-bit
x 3-bit multiplier IC.
[Home] [Contact us] [Curriculum] [Senior Projects] [Research] [People] [Links]
Copyright (c)1995-2013 Bradley University. All rights reserved.