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Sensor Interrupt and Test Circuit in VLSI
Paul Peterson and Erin Vander Laan
Advisor: Dr. V. Prasad

The S.I.T.C. is a VLSI based project that has the ability to perform self-tests on itself in addition to performing a normal task. The design is divided into two main parts: the sensor interrupt circuit and the test circuit. The sensor interrupt circuit is the 'subject to be tested' and the test circuit is the 'device that tests the subject.' The test circuit is subdivided into two parts, making a total of three distinct blocks.

  • Block 1: The sensor interrupt circuit:

  • This circuit has a three-input, two- output full adder that performs addition when operating normally. The circuit also possesses two sensors, which, if tripped, interrupt the circuit's normal functions and activate a corresponding alarm. When the sensor is reset, the circuit resumes its normal task of adding.
  • Block 2: The test circuit of the alarms:

  • This portion of the test circuit interrupts ALL functions of Block 1. It trips the sensors, purposely activating each alarm for a limited time. The test circuit interruption takes precedence over all of Block 1's interruptions, and a reset switch stops the test and returns control back to Block 1.
  • Block 3: The test circuit of the normal operation logic:

  • This portion works independent of Block 2 and interrupts all normal functions of Block 1. The circuit generates all possible inputs for the adder, compares the actual outputs with the correct values generated by a sequence generator, and gives a warning if the outputs don't match. A reset switch returns control back to Block 1.
Test vectors and fault experiments are methods of double checking the functionality of Blocks 1 and 3. Block 2's functionality is determined by inspection.
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