PPT Slide
Jarrod Luker Tim McKinney
TESTABLE VLSI CIRCUIT DESIGN FOR CELLULAR ARRAYS
- 4-BIT X 4-BIT MULTIPLIER CELL IS DESIGNED
- 4-BIT X 4-BIT MULTIPLIER IS DESIGNED AND
WILL BE SIMULATED BY 12/03/98
- SEQUENCE GENERATOR AND REGISTER
WILL BE STARTED ON 12/03/98
- DESIGN AND SIMULATION WILL BE COMPLETED
BY EARLY FEBRUARY AND WILL BE SENT FOR