PPT Slide
SUMMARY OF FINAL PROJECT
4-bit design did not fit on the allotted area of silicon. The proposed solution to this problem is to base the entire design on 3 bits.
CIRCUIT TO BE TESTED
3-BIT SEQUENCE GENERATOR
6-BIT REGISTER
3-BIT X 3-BIT MULTIPLIER
TESTABILITY FEATURES
Jarrod Luker Dr. V. Prasad Tim McKinney
TESTABLE VLSI CIRCUIT DESIGN
Previous slide
Next slide
Back to first slide
View graphic version