TESTABLE VLSI CIRCUIT DESIGN FOR CELLULAR ARRAYS
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DELIVERABLES

• PROJECT CONFIRMATION MEMO
• FUNCTIONAL DESCRIPTION
• SYSTEM BLOCK DIAGRAM
• DATASHEET
• PATENTS, STANDARDS, BIBLIOGRAPHY
• POWER POINT PRESENTATION OF SENIOR PROJECT PROPOSAL
• SENIOR DESIGN PROJECT PROPOSAL
• POWER POINT PRESENTATION OF SENIOR PROJECT PROGRESS REPORT #1
• POWER POINT PRESENTATION OF SENIOR PROJECT PROGRESS REPORT #2
• STUDENT RESEARCH EXPO POWER POINT PRESENTATION OF SENIOR PROJECT
• FINAL POWER POINT PRESENTATION OF SENIOR PROJECT

DESIGN WORK
4-BIT DESIGNS

• LOGIC WORKS DESIGN OF THE 4-BIT X 4-BIT MULTIPLIER (11-05-98)
• CMOS DESIGN OF THE 4-BIT X 4-BIT MULTIPLIER CELL (11-12-98)
• PSPICE SIMULATION OF THE 4-BIT X 4-BIT MULTIPLIER CELL (11-12-98)
• CMOS DESIGN OF THE 4-BIT X 4-BIT MULTIPLIER (12-03-98)
• PSPICE SIMULATION OF THE 4-BIT X 4-BIT MULTIPLIER (12-03-98)
• LOGIC WORKS DESIGN OF THE 4-BIT SEQUENCE GENERATOR #1 (01-13-99)
• LOGIC WORKS DESIGN OF THE 4-BIT SEQUENCE GENERATOR #2 (01-13-99)
• CMOS DESIGN OF THE D FLIP-FLOP (01-21-99)
• PSPICE SIMULATON OF THE D FLIP-FLOP (01-21-99)
• CMOS DESIGN OF THE 4-BIT SEQUENCE GENERATOR (01-28-99)
• PSPICE SIMULATON OF THE 4-BIT SEQUENCE GENERATOR (01-28-99)
• LOGIC WORKS DESIGN OF THE 8-BIT REGISTER (01-28-99)
• CMOS DESIGN OF THE 8-BIT REGISTER (01-28-99)
• PSPICE SIMULATON OF THE 8-BIT REGISTER (01-28-99)
• FINAL PAD LAYOUT (01-28-99)

3-BIT DESIGNS

• LOGIC WORKS DESIGN OF THE 3-BIT X 3-BIT MULTIPLIER (02-04-99)
• CMOS DESIGN OF THE 3-BIT X 3-BIT MULTIPLIER (02-04-99)
• PSPICE SIMULATON OF THE 3-BIT X 3-BIT MULTIPLIER (02-04-99)
• CMOS DESIGN OF THE D FLIP-FLOP (02-04-99)
• PSPICE SIMULATON OF THE D FLIP-FLOP (02-04-99)
• LOGIC WORKS DESIGN OF THE 3-BIT SEQUENCE GENERATOR (02-04-99)
• CMOS DESIGN OF THE 3-BIT SEQUENCE GENERATOR (02-11-99)
• PSPICE SIMULATON OF THE 3-BIT SEQUENCE GENERATOR (02-11-99)
• LOGIC WORKS DESIGN OF THE 6-BIT REGISTER (02-11-99)
• CMOS DESIGN OF THE 6-BIT REGISTER (02-11-99)
• PSPICE SIMULATON OF THE 6-BIT REGISTER (02-11-99)
• FINAL PAD LAYOUT (02-16-99)
• PSPICE SIMULATION OF THE FINAL LAYOUT (5MHz) (02-25-99)
• PSPICE SIMULATION OF THE FINAL LAYOUT (500kHz) (04-08-99)
• PSPICE SIMULATION OF THE FINAL LAYOUT (50kHz) (04-08-99)
• PSPICE SIMULATION OF THE FINAL LAYOUT (5kHz) (04-15-99)
• PSPICE SIMULATION OF THE FINAL LAYOUT (.5kHz) (04-15-99)

MISCELLANEOUS VLSI WORK

• VLSI DESIGN RULES
• CMOS GATES
• PSPICE PROBE OF A FULL ADDER

rekul@bobcat.bradley.edu ©1999 Luker Designs Inc.