United States Patent 5,754,561
Masui
May 19, 1998

Large scale integrated circuit equipped with a normal internal logic testing circuit and unconnected/substandard solder testing circuit

An LSI equipped with an internal logic circuit which outputs a normal external output signal to the outside of the LSI during normal operation, and which outputs a test signal which is used for internal logic testing. An LSI is also equipped with an internal logic and unconnected/substandard-solder testing circuit which performs both internal logic testing and unconnected/substandard-solder testing. This internal logic and unconnected/substandard-solder testing circuit is equipped with an internal logic testing logic circuit into which the abovementioned test signals are input, an unconnected/substandard-solder testing logic circuit to which prescribed input and output terminals of the abovementioned LSI are connected, and one output logic circuit which controls the output of the above-mentioned internal logic testing logic circuit and the output of the abovementioned unconnected/substandard-solder testing logic circuit. Then, the abovementioned normal external output signal from the abovementioned internal logic circuit is supplied directly to the external output terminal of the LSI. Since this normal external output signal is output directly from the internal logic circuit to the external output terminal, without passing through gate circuits and the like, signal delays do not occur. Furthermore, it is possible to reduce the number of gate circuits because the circuits, which perform the internal logic testing and the unconnected/substandard-solder testing, have been made into a common circuit.

Inventors: Masui; Kazuhiro (Yokohama, JP).
Assignee: Fujitsu Limited (Kawasaki, JP).
Appl. No.: 863,520
Filed: May 27, 1997

Method of generating test sequence and apparatus for generating test sequence

In a method of generating a test sequence for testing a stuck-at fault supposed in a sequential circuit as a test circuit, the number of flip-flops which can be replaced with scan flip-flops among flip-flops included in the circuit under test is initially specified in the first step. Next, in the second step, there is calculated, for each of the flip-flops included in the circuit under test, the sequential depth of a clock defined as the minimum number of flip-flops that are passed through while the input side from the clock input terminal of the flip-flop is traced until an external input pin is reached. In the third step, flip-flops are identified with scan flip-flops by the number specified in the first step in the order of decreasing sequential depth of a clock, which was calculated in the second step.

Inventors: Hosokawa; Toshinori (Osaka, JP).
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP).
Appl. No.: 758,835
Filed: Dec. 4, 1996

United States Patent 5,640,142
Matatall, Jr., et. al.
Jun. 17, 1997

Alarm system testing circuit

A testing circuit for an alarm system is disclosed. The testing circuit is operable in an alarm system that includes a microphone for receiving an audio sound and a detector/generator for detecting audio characteristics in the audio sound corresponding to breaking glass and for generating an alarm signal in response thereto. The audio characteristics corresponding to breaking glass include first and second frequency components in timed relation, wherein the first frequency must be detected prior to the second frequency for an alarm to be generated. The testing circuit includes a trigger circuit for receiving the audio signal and for detecting the first-frequency component thereof, the trigger circuit activating the detector/generator in response to detection of the first-frequency component; a test circuit for periodically generating a test audio sound at the second frequency, the trigger circuit remaining operable to detect the first-frequency component during generation of the test audio sound; and circuitry operable during generation of the test audio sound for detecting the test audio sound and for (a) resetting the test circuit in response to detection of the test audio sound and (b) generating a fault signal upon non-detection of the test audio sound. The glass-break sensor is not disabled during a self-test and utilizes a test sound at a frequency that is normally used by the sensor for detecting breaking glass.

Inventors: Matatall, Jr.; Richard Lewis (Springfield, MA); Turek, Jr.; Joseph John (Wilbraham, MA); Turek; Stanley Joseph (E. Longmeadow, MA).
Assignee: Pittway Corporation (Syosset, NY).
Appl. No.: 682,390
Filed: Jul. 17, 1996

United States Patent 5,642,052
Earle
Jun. 24, 1997

Hand-held tester for receptacle ground fault circuit interrupters

An electrical test device for testing the function of a receptacle ground fault circuit interrupter. The tester plugs into a receptacle and includes a current source, timer, testing circuit, and display. The current source introduces a substantially constant fault current between the hot and ground leads of the receptacle. Once this occurs, the timer begins counting time and generates a time count signal. The test circuit receives the time count signal and determines whether the interrupter enters a tripped state within a designated time. The testing circuit responsively generates a trip indicator signal reflecting whether or not the ground fault interrupter circuit tripped within the designated trip time. The display means receives the trip indicator signal and responsively indicates whether the interrupter functioned properly by tripping the designated trip time. Further, the tester includes a volt meter and wiring status indicator to advise the user of the voltage between the hot and neutral lines of the receptacle as whether the receptacle has been incorrectly connected to power lines.

Inventors: Earle; Kent L. (Woodridge, IL).
Assignee: Etcon Corporation (Burr Ridge, IL).
Appl. No.: 461,427
Filed: Jun. 5, 1995

United States Patent 5,825,785
Barry, et. al.
Oct. 20, 1998

Serial input shift register built-in self test circuit for embedded circuits

A highly functional built in self test circuit for embedded compiled macros is useful for testing embedded compiled macros having differing parameters. The built in self test circuit receives a scan vector that describes the parameters of the embedded compiled macro that is to be tested. For, example, the number and width of words stored in a read only memory (ROM) are scanned into the built in self test circuit for controlling the test sequences. A state machine within the built in self test circuit cycles through test vector generation, test vector application, data output scanning and compression for signature analysis. Parallel outputs of the embedded compiled devices are serialized so that regardless of the number of outputs, a serial input shift register can be used for signature generation.

Inventors: Barry; Robert L. (Essex Junction, VT); Chickanosky; John D. (South Burlington, VT); Oakland; Steven F. (Colchester, VT); Ouellette; Michael R. (Westford, VT).
Assignee: Internaitonal Business Machines Corporation (Armonk, NY).
Appl. No.: 653,572
Filed: May 24, 1996

United States Patent 5,825,783
Momohara
Oct. 20, 1998

Semiconductor integrated circuit device with large-scale memory and controller embedded on one semiconductor chip and method of testing the device

A semiconductor integrated circuit device comprises, on a semiconductor chip, a large-scale memory as a main memory, a controller for controlling at least inputting data from the outside of the chip to the large-scale memory, and outputting data from the large-scale memory to the outside of the chip, and a self-test circuit for testing the large-scale memory. The self-test circuit includes a rewritable EEPROM, into which a self-test sequence is written. The self-test circuit tests the large-scale memory in accordance with the self-test sequence written in the EEPROM.

Inventors: Momohara; Tomomi (Yokohama, JP).
Assignee: Kabushiki Kaisha Toshiba (Tokyo, JP).
Appl. No.: 757,287
Filed: Nov. 27, 1996

United States Patent 5,815,511
Yamamoto
Sept. 29, 1998

Semiconductor integrated circuit equipped with test circuit

An integrated circuit device equipped with a test circuit includes a plurality of input/output terminals, an input terminal, and an internal circuit for receiving input data via the plurality of input/output terminals and outputting output data. The test circuit permits data exchange among the input/output terminals, the input terminal and the internal circuit. The test circuit preferably operates in a normal mode to supply input data to the internal circuit through the input/output terminals, and supply output data from the internal circuit through the input/output terminals. The test circuit further operates in a test mode to supply test input data to the internal circuit through one of the input terminal and the input/output terminals. The test circuit further supplies test output data that is output from the internal circuit to one of the input terminal and the input/output terminals which differ from the test input data supplied terminal.

Inventors: Yamamoto; Yasuhiro (Kasugai, JP).
Assignee: Fujitsu Limited (Kanagawa, JP).
Appl. No.: 728,978
Filed: Oct. 11, 1996

United States Patent 5,734,661
Roberts, et. al.
Mar. 31, 1998

Method and apparatus for providing external access to internal integrated circuit test circuits

An integrated circuit includes an integrated circuit die mounted in a package having a plurality of externally accessible contacts. A functional circuit, such as a memory circuit, is formed on the integrated circuit die and is coupled through bonding pads to the external contacts of the integrated circuit. A test circuit is also formed on the integrated circuit die to allow performance parameters to be determined by performing tests on the test circuit when the test circuit is in wafer form before packaging. To allow tests to be performed on the test circuit after packaging, a switch circuit formed on the integrated circuit die selectively couples input/output terminals of the test circuit to respective bonding pads that are connected to the externally accessible contacts. The switch circuit is operated by a switch controller, which may be a decoder that responds to a pattern of signals or a sequence of signals applied to the externally accessible contacts or an overvoltage detector that responds to a voltage outside a range of operating voltages for the functional circuit.

Inventors: Roberts; Gordon (Meridian, ID); Miller, Jr.; James E. (Boise, ID).
Assignee: Micron Technology, Inc. (Boise, ID).
Appl. No.: 717,133
Filed: Sept. 20, 1996

United States Patent 5,729,553
Motohara
Mar. 17, 1998

Semiconductor integrated circuit with a testable block

Three blocks cascaded to one another in an LSI, namely, an input module, a macro module and an output module, are independently tested. A first test circuit is formed with a first multiplexer interposed between the macro module and the output module, and a second multiplexer and a first control register interposed between the input module and the macro module. A second test circuit is similarly formed with third and fourth multiplexers and a second control register. A test input signal of a plurality of bits is supplied to the first multiplexer, and a latched signal of the first control register is supplied to the third multiplexer, thereby allowing a latched signal of the second control register to be output as a test output signal for observation. Thus, testing techniques requiring a small additional circuit and a small number of additional wires for the test can be provided.

Inventors: Motohara; Akira (Hyogo, JP).
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP).
Appl. No.: 684,066
Filed: Jul. 19, 1996

United States Patent 5,671,233
Kamada
Sept. 23, 1997

Integrated circuit incorporating a test circuit

Disposed in an integrated circuit is a test circuit having: a plurality of tristate buffers each for supplying, in a test mode, a charging current to a stray capacitance of a corresponding wire on a printed circuit board through a corresponding signal terminal of the integrated circuit; and a plurality of exclusive-OR gates each for supplying a logical signal having a pulse width indicative of a time interval between an input transition time and an output transition time of a corresponding tristate buffer. A difference in capacitance between a state where a signal terminal is being properly electrically connected to a wire on the printed circuit board and a state where the signal terminal is being improperly electrically connected thereto, is converted into a difference in pulse width of a logical signal, based on which a defective soldering of open failure in the signal terminal is detected.

Inventors: Kamada; Takehiro (Osaka, JP).
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP).
Appl. No.: 646,564
Filed: May 8, 1996

United States Patent 5,748,639
Choi, et. al.
May 5, 1998

Multi-bit test circuits for integrated circuit memory devices and related methods

A method for testing a plurality of data bits includes the steps of accepting the plurality of data bits at the test circuit, and comparing first and second data bits from the plurality of data bits to determine if the first and second data bits have a common data value. A first comparison signal is generated responsive to the comparison of the first and second data bits. The first comparison signal has a first logic state when the first and second data bits have a common data value and a second logic state when the first and second data bits have different data values. Third and fourth data bits from the plurality of data bits are compared to determine if the third and fourth data bits have a common data value. A second comparison signal is generated responsive to the comparison of the third and fourth data bits wherein the second comparison signal has the first logic state when the third and fourth data bits have a common data value and the second logic state when the third and fourth data bits have different data values.

Inventors: Choi; Myung-chan (Kyungki-do, KR); Park; Churoo (Kyungki-do, KR).
Assignee: Samsung Electronics Co., Ltd. (Suwon, KR).
Appl. No.: 637,358
Filed: Apr. 24, 1996

United States Patent 5,646,897
Yukutake, et. al.
Jul. 8, 1997

Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels

A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.

Inventors: Yukutake; Seigou (Kodaira, JP); Iwamura; Masahiro (Hitachi, JP); Mitsumoto; Kinya (Tamamura-machi, JP); Akioka; Takashi (Akishima, JP); Akiyama; Noboru (Hitachinaka, JP).
Assignee: Hitachi, Ltd. (Tokyo, JP).
Appl. No.: 426,384
Filed: Apr. 21, 1995

United States Patent 5,615,216
Saeki
Mar. 25, 1997

Semiconductor integrated circuit including test circuit

A first test circuit is connected to one end of a first wiring line, and a second test circuit is connected to one end of a second wiring line. The second wiring line serves as a data bus. N-channel MOS transistors, connected in series, are provided between the first and second wiring lines and located below a third wiring line. The transistors are set in a conductive state by a gate control signal from a test control circuit in a test mode, and are set in an OFF state in a normal operation mode. In the normal operation mode, the capacitance between the first and second wiring lines is small and does not adversely affect the operation speed of an integrated circuit.

Inventors: Saeki; Yukihiro (Yokohama, JP).
Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP).
Appl. No.: 262,835
Filed: Jun. 21, 1994

United States Patent 5,612,962
Sato, et. al.
Mar. 18, 1997

Pin-scan-in type LSI logic circuit, pin-scan-in system driving circuit, and method of testing circuit-mounting substrates

A pin-scan-in system driving circuit drives a pin-scan-in circuit to test short-circuit of the wirings or breaking of the wirings in the circuit-mounting substrate, and this circuit is driven using a reduced number of gates. The pin-scan-in system driving circuit drives the pin-scan-in circuit provided in an LSI logic circuit, and the LSI logic circuit is provided with a pin-scan-in circuit selector which selects the pin-scan-in circuit and a selected condition-holding circuit which holds the condition selected by the pin-scan-in circuit selector.

Inventors: Sato; Toshiro (Kawasaki, JP); Yamamoto; Kunitoshi (Kawasaki, JP); Adachi; Hiroyuki (Kawasaki, JP).
Assignee: Fujitsu Limited (Kanagawa, JP).
Appl. No.: 70,412
Filed: Jun. 4, 1993

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