Data Sheet


Although the bulk of the project is done using VLSI (Very Large Scale Integration) with the design program L-Edit, the sensor interrupt and test circuit must first be simulated at a broader level with LogicWorks and implemented with existing TTL chips and other ICs. Once the design is accomplished with ICs, it can be broken down to the VLSI level.

The following is a list of the ICs used, their pinouts, and their I/O parameters as listed in a TTL Logic book and other standard data sheets. Please refer to the Functional Description and Block Diagram for more information.

(4 bit) Latch (All latches)
SN74LS373-74 Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

- Power Supply (Vcc): 5V
- Enable Latch or Clock (C): 1MHz Crystal Oscillator (0V and 5V levels)

(2:4) Demultiplexer (All Demuxes)
SN74LS139A Dual 2-Line to 4-Line Decoders

- Power Supply (Vcc): 5V

(4bit) Counter (Counters T1,T2)
SN74LS93 4-Bit Binary Counters

- Power Supply (Vcc): 5V

- Clock A (CKA): Various Frequencies of Input Pulses (0V and 5V Levels)
- Clock B (CKB): Connected to QA, Least Significant Bit of Output

Divide-By-Ten Counter (Counter controls; slows down the 7493 counting rate)
SN74LS90 4-Bit Decade Counters

- Power Supply (Vcc): 5V

- Clock A (CKA): Various Frequencies of Input Pulses (0V and 5V Levels)
- Clock B (CKB): Connected to QA, Least Significant Bit of Output
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