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Digital Phase-Locked Loop
Xavier Aragones and J. Paclik
Advisors: Dr. T. L. Stewart and Dr. I. S. Ahn

The phase-locked loop (PLL) is an essential part of many communications systems, performing such tasks as FM detection, coherent AM detection, frequency multiplication and frequency synthesis. The PLL is particularly useful in determining the phase relationship of two signals. The PLL may be implemented by using analog circuitry, the analog PLL (APLL), or by using digital circuitry, the digital PLL (DPLL). With advances in microprocessor technology, the DPLL may now be implemented on digital signal processors, specialized processors designed specifically for signal manipulation. The implementation of a DPLL using a digital signal processor offers many advantages over the APLL, such as adaptive filtering and adaptive frequency selection. 

The goal of our project was to implement a basic DPLL, consisting of a phase comparator, loop filter and VCO. We will discuss the advantages of the DPLL over the APLL as well as some of the peculiarities of digital implementation. Lastly, we will discuss the performance of our DPLL, such as capture and lock range, and propose areas of future interest.

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